This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Integrated circuits (ICs) containing non-volatile memory typically employ high voltages to force charge into and out of floating-gate memory storage elements. To produce sufficient electric field across the floating gates without exceeding the breakdown limits of the technology, device terminals may be charged to opposite polarities with respect to the substrate, often by high-impedance charge pumps. Flash memory technology uses this technique when erasing the memory array. Large circuit capacitances, including the capacitance that couples arrays of memory gates to their respective source, drain, and well terminals, thereby charge to voltages that can approach the positive and negative breakdown limits of the IC technology.
Removing charge stored on high-voltage nodes after erasing is conventionally done by connecting all array terminals to ground through discharge transistors. But this can cause terminals to overshoot above safe operating limits. The overshoot problem arises because only part of the charge stored on high-voltage nodes is on capacitance that is coupled to the IC's substrate. A significant portion of the charge is stored on capacitance coupled between the gates and bodies of the memory cells, which were charged to opposite high-voltage polarities with respect to substrate during the prior erase.
The overshoot problem cannot be solved simply by attempting to discharge one terminal at a time toward the substrate voltage, as this causes the other end of each coupled capacitance to move in the same direction. Discharging the array well terminal that was charged to positive polarity pulls the gate, which was charged to negative polarity, still more negative. Discharging the negative gate terminal toward ground pulls the well terminal more positive. The overshoots that result from this coupling can cause the switching transistors to over-stress or snap back, potentially causing catastrophic damage to the switching transistors.
The conventional way to discharge capacitances has been to simultaneously turn on transistors that connect each circuit node to the common ground. An attempt is made to provide substantially equal impedance paths to ground from all high-voltage nodes. The timing skew between activation of the various discharge transistors must be carefully controlled to minimize overshoot. Also, the relative strengths of the discharging transistor channels must be carefully adjusted to carry the sum of displacement currents from all capacitance branches attached to each node. This balance of discharge-path sizing and precise timing control is critical to reduce overshoot to acceptable levels, yet is increasingly difficult to achieve with sufficient accuracy in ever-larger memory arrays having a variable number of storage elements with lower over-voltage tolerances, as in newer generations of flash memories on integrated devices such as field-programmable gate arrays (FPGAs).
FIG. 1 is a schematic block diagram representing a voltage discharge (VD) system 100 according to the prior art. VD system 100 has two voltage discharge subsystems: a slow VD subsystem 110 and a fast VD subsystem 120. VD system 100, which is part of a larger integrated circuit, such as an FPGA, is used to discharge high voltages that are generated, e.g., to erase non-volatile memory that is also part of the IC. Before discussing the discharge operations of VD system 100, the IC's charging operations will first be discussed.
In FIG. 1, the nodes positive_pump and negative_pump represent the positive and negative output terminals, respectively, of a high-impedance positive and negative charge pump (not shown) implemented in the IC. In addition, device i26 represents an entire memory array containing (in this particular case) 488,320 non-volatile (e.g., flash) memory cells, where the node N1T collectively represents the (possibly) common-voltage word lines connected to the gates of the cells in that memory array, and the node array_well collectively represents the (possibly) common-voltage wells (e.g., both the P-well body and the N-well (isolation island) typically connected beneath each cell) in that memory array. In this exemplary array, each cell resides in a double-well structure consisting of a P-well inside an N-well, where both wells are tied together, inside a P-substrate.
Capacitor neg_filter models a decoupling capacitor placed between the node negative_pump and ground (Vss), which capacitor may be used to reduce noise and ripple components on the negative supply.
In order to erase the memory array, with the node N1T connected to the charge pump's negative terminal negative_pump (via the word lines and via switches not shown in FIG. 1), erase control signal erase_n is driven low (e.g., to Vss), which turns on the device “precharger”, thereby connecting the charge pump's positive terminal positive_pump to the node array_well. In one implementation, for erasure, the charge pump applies a positive voltage (Vpp) of about +8.5v to drive the flash cells' P-well and N-well terminals above the substrate potential Vss, where the positive logic supply voltage level Vcc is about 1.2v, and the charge pump applies a negative voltage (Vneg) of about −8.5v to the flash cells' gate terminals below the substrate potential. The high-voltage differential (about 17v) between the positive node array_well and the negative node N1T erases the memory cells in the array.
After the memory has been erased, erase control signal erase_n is driven high (e.g., Vpp) to turn off the precharger device, thereby disconnecting the node array_well from the terminal positive_pump. At this point, however, the capacitances on node array_well retain their charged state, which maintains array_well at a high positive potential with respect to ground, and the capacitances on node negative_pump retain their charged state, which maintains negative_pump at a high negative potential.
In order to discharge those high positive and negative charges, VD system 100 implements a two-stage discharge sequence. During the first stage, slow VD subsystem 110 is turned on to slowly discharge the node negative_pump towards ground (Vss). During the second stage, with slow VD subsystem 110 either turned off or left on, fast VD subsystem 120 is turned on to quickly discharge the node array_well toward ground, while accelerating the discharge of the node negative_pump towards ground. Performing the first stage prior to the second stage reduces the displacement current through gate-coupling capacitance that could otherwise produce undesirable levels of overshoot at the node array_well.
In particular, prior to initiation of the first stage, the slow discharge control signal slow_discharge is low, which results in device i38 of slow VD subsystem 110 being off, thereby disconnecting that path from the node negative_pump to ground. To initiate the first stage, slow discharge control signal slow_discharge is driven high (Vcc), which turns on device i38. This pulls node “sdis” to Vcc, which causes source-follower device i37 to begin pulling node negative_pump upward (less negative) at a rate determined by the capacitances on negative_pump and the channel impedances of i37, i38, and i58. PMOS device i38 prevents node sdis from pulling below ground, to prevent forward-biasing the NMOS drain to P-substrate junctions in inverter i58; its channel impedance is made relatively large to maintain a slow pullup rate on negative_pump, Triple-well NMOS device i37 prevents negative_pump from pulling above ground by cutting off as negative_pump approaches its grounded gate voltage.
During the first stage of discharge operations, the voltage at the node negative_pump is monitored by control circuitry (not shown in FIG. 1). When that control circuitry determines that the voltage at the node negative_pump has discharged beyond a set detection level, then the second stage of discharge operations is initiated.
In particular, prior to initiation of the second stage, the fast discharge control signals clamp_pos and clamp_neg are set low (e.g., Vss) and high (e.g., Vcc), respectively. With control signal clamp_pos low, devices i60, i50, and i51 are all off, thereby disconnecting that path from the node array_well to ground. Similarly, with control signal clamp_neg high, devices i30 and i142 are both off, thereby disconnecting that path from the node negative_pump to ground.
To initiate the second stage, control signals clamp_pos and clamp_neg are driven high (e.g., Vpp) and low (e.g., Vss), respectively. Driving control signal clamp_pos high turns on devices i60, i50, and i51, thereby connecting the node array_well to ground. Driving control signal clamp_neg low turns on device i30, which drives the node neg_gate high, which, in turn, turns on device i142, thereby connecting the node negative_pump to ground. Transistors i30 and i142 and resistor i32 form a circuit that clamps a negative potential at node negative_pump to ground (Vss) under control of the positive-logic level control signal clamp_neg.
Although the reverse displacement current from the positive discharge path (i.e., from array_well to ground via devices i60, i50, and i51) causes negative overshoot of the node negative_pump, the reduced voltage on the node negative_pump provides enough headroom to avoid over-stress there. However, this approach slows but does not completely eliminate the positive overshoot problem. As such, the transistors used to discharge the node array_well must be built to withstand particularly high voltages, usually by stacking multiple devices in series (cascode arrangement). This method also adds complexity by requiring a discharge-level sensor, and the slow-discharge rate must be carefully adjusted for each load situation to obtain an acceptable trade-off between positive and negative overshoots and the added discharge time.